US 12,408,331 B2
Memory device and manufacturing method thereof
Huixian Lai, Quanzhou (CN); Chao-Wei Lin, Quanzhou (CN); and Chia-Yi Chu, Quanzhou (CN)
Assigned to Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou (CN)
Filed by Fujian Jinhua Integrated Circuit Co., Ltd., Quanzhou (CN)
Filed on Mar. 23, 2023, as Appl. No. 18/125,142.
Application 18/125,142 is a continuation of application No. 17/151,669, filed on Jan. 19, 2021, granted, now 11,641,736.
Claims priority of application No. 202020139552.1 (CN), filed on Jan. 21, 2020.
Prior Publication US 2023/0232620 A1, Jul. 20, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/50 (2023.02) [H10B 12/01 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a substrate, having a plurality of active areas and an isolation trench structure formed therein;
at least one first isolation pillar and a plurality of second isolation pillars formed on the substrate; and
a shielding layer directly contacting a top surface of one of the second isolation pillars;
wherein the at least one first isolation pillar and the plurality of second isolation pillars are used for define a plurality of node contact windows, wherein the second isolation pillars and the node contact windows are arranged in an alternating configuration, and wherein a height of the first isolation pillar is higher than a height of the second isolation pillar, wherein at least one node contact window is disposed between the first isolation pillar and the second isolation pillar, wherein the first isolation pillar, the second isolation pillars, and the shielding layer are made of insulating materials, and a top surface of the shielding layer is higher than a top surface of the first isolation pillar.