| CPC H10B 12/50 (2023.02) [H10B 12/09 (2023.02); H10B 12/315 (2023.02)] | 20 Claims |
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1. A semiconductor memory device, comprising:
a substrate including a memory cell region, a peripheral region laterally enclosing the memory cell region, and an intermediate region laterally between the memory cell region and the peripheral region;
a device isolation pattern on the substrate in the memory cell region and defining active portions in the memory cell region;
a partitioning pattern on the substrate in the intermediate region;
a plurality of bit lines on the substrate in the memory cell region and the intermediate region and extending in a first direction, the bit lines extending to a boundary between the intermediate region and the peripheral region;
storage node contacts on the substrate in the memory cell region and each storage node contact filling a lower portion of a space between first respective pairs of the bit lines;
landing pads on the storage node contacts, respectively;
dummy storage node contacts on the substrate in the intermediate region, in contact with the partitioning pattern, and each dummy storage node contact filling a lower portion of a space between second respective pairs of the bit lines;
dummy landing pads on the dummy storage node contacts, respectively; and
at least one dam structure on the substrate in the intermediate region and extending in the first direction, the at least one dam structure having a bar shape when viewed in a plan view,
wherein the dummy landing pads are spaced apart from one another and from an edge portion of the at least one dam structure in a second direction perpendicular to the first direction and include metal.
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