US 12,408,329 B2
Method for manufacturing semiconductor structure, semiconductor structure, and semiconductor memory
Jingwen Lu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 5, 2023, as Appl. No. 18/150,306.
Application 18/150,306 is a continuation of application No. PCT/CN2022/071111, filed on Jan. 10, 2022.
Claims priority of application No. 202111301855.4 (CN), filed on Nov. 4, 2021.
Prior Publication US 2023/0157008 A1, May 18, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/485 (2023.02) [H10B 12/02 (2023.02); H10B 12/482 (2023.02)] 15 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a plurality of active areas;
forming a plurality of bit line contact mask structures above the plurality of active areas, wherein each of the plurality of bit line contact mask structures at least covers one active area terminal;
performing downward etching along the plurality of bit line contact mask structures to form a node contact hole in the active area terminal, and filling the node contact hole with a semiconductor material to form a first node contact structure; and
forming a plurality of bit line structures above the plurality of active areas, and filling continuously gaps between the plurality of bit line structures with the semiconductor material until a second node contact structure is formed, wherein the first node contact structure and the second node contact structure collectively form a node contact structure.