US 12,408,327 B2
Semiconductor structure and method for manufacturing same
Yexiao Yu, Hefei (CN); Longyang Chen, Hefei (CN); and Zhongming Liu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 30, 2023, as Appl. No. 18/161,124.
Application 18/161,124 is a continuation of application No. PCT/CN2022/070400, filed on Jan. 5, 2022.
Claims priority of application No. 202111311525.3 (CN), filed on Nov. 8, 2021.
Prior Publication US 2023/0180465 A1, Jun. 8, 2023
Int. Cl. H01L 21/311 (2006.01); H01L 21/308 (2006.01); H10B 12/00 (2023.01)
CPC H10B 12/482 (2023.02) [H01L 21/3086 (2013.01); H01L 21/31144 (2013.01); H10B 12/485 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor structure, comprising:
forming a spin on hard mask layer on a base, wherein a plurality of active areas arranged at intervals are provided in the base, a plurality of bit lines arranged at intervals and extending in a first direction are provided on the base, each of the bit lines is electrically connected to at least one of the active areas, and the spin on hard mask layer is filled between the bit lines and covers the bit lines;
removing part of the spin on hard mask layer to form a plurality of first trenches arranged at intervals and extending in a second direction;
forming first sacrificial layers in the first trenches, wherein each of the first sacrificial layers is filled in each of the first trenches;
removing the spin on hard mask layer between the first sacrificial layers to form second trenches;
forming first supporting layers in the second trenches, wherein each of the first supporting layers is filled in each of the second trenches; and
removing the first sacrificial layers and elongating the first trenches located between adjacent bit lines to the active areas.