US 12,408,326 B2
Semiconductor structure and formation method thereof, and memory
Guangsu Shao, Hefei (CN); Deyuan Xiao, Hefei (CN); and Yunsong Qiu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Aug. 31, 2022, as Appl. No. 17/899,627.
Application 17/899,627 is a continuation of application No. PCT/CN2022/103375, filed on Jul. 1, 2022.
Claims priority of application No. 202210709072.8 (CN), filed on Jun. 21, 2022.
Prior Publication US 2023/0413535 A1, Dec. 21, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/482 (2023.02) [H10B 12/05 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor structure, comprising:
providing a base substrate, the base substrate comprising a substrate and an insulating material layer, the substrate comprising a plurality of first trenches arranged at intervals along a first direction, and the insulating material layer filling each of the plurality of first trenches;
etching the base substrate to form a plurality of second trenches arranged at intervals along a second direction, the second direction intersecting with the first direction;
removing a part of a material of the substrate below the plurality of second trenches to form third trenches below the plurality of second trenches, the third trenches penetrating through each of the plurality of second trenches;
filling a conductive material into the third trenches to form bit line structures; and
forming word line structures in the plurality of second trenches, the word line structures being insulated from the bit line structures.