| CPC H10B 12/315 (2023.02) [H10B 12/482 (2023.02)] | 20 Claims |
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1. A semiconductor memory device comprising:
a substrate;
a conductive line extending in a first horizontal direction above the substrate;
an isolation insulating layer comprising a channel trench extending in a second horizontal direction intersecting with the first horizontal direction and extending from an upper surface to a lower surface of the isolation insulating layer, above the conductive line;
a channel structure disposed above the conductive line;
a gate electrode extending in the second horizontal direction, in the channel trench;
a capacitor structure above the isolation insulating layer; and
a contact structure between the channel structure and the capacitor structure,
wherein the channel structure comprises an amorphous oxide semiconductor layer disposed in the channel trench above the conductive line, and an upper crystalline oxide semiconductor layer between the amorphous oxide semiconductor layer and the contact structure.
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