US 12,408,321 B2
3D horizontal memory cell with sequential 3D vertical stacking
Mark I. Gardner, Cedar Creek, TX (US); H. Jim Fulford, Marianna, FL (US); and Partha Mukhopadhyay, Jacksonville, FL (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on Dec. 5, 2022, as Appl. No. 18/075,242.
Claims priority of provisional application 63/320,457, filed on Mar. 16, 2022.
Prior Publication US 2023/0301062 A1, Sep. 21, 2023
Int. Cl. H10D 62/00 (2025.01); H01L 25/065 (2023.01); H10B 12/00 (2023.01); H10D 30/67 (2025.01); H10D 62/13 (2025.01); H10D 62/17 (2025.01)
CPC H10B 12/30 (2023.02) [H01L 25/0657 (2013.01); H10B 12/03 (2023.02); H10B 12/05 (2023.02); H10D 30/6735 (2025.01); H10D 62/151 (2025.01); H10D 62/235 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a memory cell unit positioned over a substrate, wherein the memory cell unit comprises a transistor and a capacitor,
wherein the capacitor comprises:
an inner conductor,
a capacitor dielectric all around the inner conductor,
an outer conductor all around the capacitor dielectric, and
dielectric support structures below the inner conductor,
where the capacitor is elongated in a length direction parallel to a working surface of the substrate, and the dielectric support structures are spaced along the length direction,
wherein the transistor comprises:
a channel structure,
a gate structure all around the channel structure, and
source/drain (S/D) regions on opposing ends of the channel structure.