US 12,408,319 B2
Semiconductor structure including bit lines and fabrication method thereof
Kang You, Hefei (CN); and Tangyu Pan, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 25, 2022, as Appl. No. 17/952,256.
Claims priority of application No. 202210925007.9 (CN), filed on Aug. 2, 2022.
Prior Publication US 2024/0049444 A1, Feb. 8, 2024
Int. Cl. H10B 12/00 (2023.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10B 12/09 (2023.02) [H01L 21/31116 (2013.01); H01L 21/76831 (2013.01); H10B 12/482 (2023.02); H10D 84/0147 (2025.01); H10D 84/038 (2025.01)] 12 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a plurality of bit lines arranged at intervals along a first direction on the substrate, a width of a top of each of the plurality of bit lines being greater than a width of a bottom of each of the plurality of bit lines;
forming an initial isolation spacer covering each of the plurality of bit lines, the initial isolation spacer comprising a first initial isolation layer, a second isolation layer and a third initial isolation layer stacked, the first initial isolation layer covering the plurality of bit lines, the second isolation layer being positioned between the first initial isolation layer and the third initial isolation layer, and a top surface of the second isolation layer being lower than a top surface of the first initial isolation layer; and
removing the initial isolation spacer positioned on the substrate between two adjacent ones of the plurality of bit lines, wherein a remaining portion of the initial isolation spacer forms an isolation spacer;
wherein the forming the plurality of bit lines arranged at intervals along the first direction on the substrate comprises:
forming a plurality of initial bit lines arranged at intervals along the first direction on the substrate, each of the plurality of initial bit lines comprising an initial bit line conductive layer and a bit line insulating layer stacked, and a width of the initial bit line conductive layer being equal to a width of the bit line insulating layer; and
removing a portion of width of the initial bit line conductive layer along the first direction, a remaining part of the initial bit line conductive layer constituting a bit line conductive layer, and a first stepped surface being formed between the bit line conductive layer and the bit line insulating layer;
wherein the initial bit line conductive layer comprises an initial contact layer, an initial barrier layer and an initial conductive layer sequentially stacked; and the removing a portion of width of the initial bit line conductive layer along the first direction comprises:
removing a portion of width of each of the initial conductive layer and the initial barrier layer along the first direction by means of a first etching process, to form an intermediate conductive layer and an intermediate barrier layer stacked; and
removing a portion of width of each of the intermediate conductive layer, the intermediate barrier layer, and the initial contact layer along the first direction by means of a second etching process, to form the plurality of bit lines;
wherein the second etching process comprises dry etching, etching gases of the second etching process comprise chlorine gas and nitrogen trifluoride, and a ratio of the chlorine gas to the nitrogen trifluoride is 3:1 to 1:1.