US 12,408,317 B2
SRAM macro design architecture
Saurabh P. Sinha, Austin, TX (US); Shahzad Nazar, Fremont, CA (US); Xin Miao, Saratoga, CA (US); and Emre Alptekin, San Jose, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Aug. 11, 2023, as Appl. No. 18/448,634.
Claims priority of provisional application 63/376,800, filed on Sep. 23, 2022.
Claims priority of provisional application 63/376,802, filed on Sep. 23, 2022.
Claims priority of provisional application 63/376,796, filed on Sep. 23, 2022.
Claims priority of provisional application 63/376,799, filed on Sep. 23, 2022.
Prior Publication US 2024/0107738 A1, Mar. 28, 2024
Int. Cl. H10B 10/00 (2023.01); H01L 23/528 (2006.01); H10D 30/63 (2025.01); H10D 64/23 (2025.01); H10D 64/27 (2025.01); H10D 84/85 (2025.01); H10D 89/10 (2025.01)
CPC H10B 10/125 (2023.02) [H01L 23/5286 (2013.01); H10B 10/18 (2023.02); H10D 30/63 (2025.01); H10D 64/252 (2025.01); H10D 64/518 (2025.01); H10D 84/85 (2025.01); H10D 84/856 (2025.01); H10D 89/10 (2025.01); H10B 10/12 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A memory apparatus, comprising:
a plurality of bit cells, wherein the bit cells include a first set of first transistors formed in a first transistor region and a second set of second transistors formed in a second transistor region, the second transistor region being positioned below the first transistor region in a vertical dimension perpendicular to the plurality of bit cells, wherein the plurality of bit cells are divided into at least a first array of bit cells and a second array of bit cells;
a first metal layer located below the plurality of bit cells in the vertical dimension, wherein the first metal layer includes first routing coupled to bitline outputs of the first array of bit cells;
a second metal layer located above the plurality of bit cells in the vertical dimension, wherein the second metal layer includes second routing coupled to bitline outputs of the second array of bit cells;
a first column input/output logic cell coupled to the bitline outputs of the first array of bit cells by the first routing; and
a second column input/output logic cell coupled to the bitline outputs of the second array of bit cells by the second routing;
wherein the first array of bit cells are positioned further away from the first column input/output logic cell and the second column input/output logic cell than the second array of bit cells.