US 12,408,316 B2
Memory array circuit and method of manufacturing same
Hidehiro Fujiwara, Hsinchu (TW); Chih-Yu Lin, Hsinchu (TW); Hsien-Yu Pan, Hsinchu (TW); Yasutoshi Okuno, Hsinchu (TW); Yen-Huei Chen, Hsinchu (TW); and Hung-Jen Liao, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jun. 27, 2024, as Appl. No. 18/756,363.
Application 17/325,641 is a division of application No. 16/457,553, filed on Jun. 28, 2019, granted, now 11,018,142, issued on May 25, 2021.
Application 18/756,363 is a continuation of application No. 18/304,301, filed on Apr. 20, 2023, granted, now 12,029,023.
Application 18/304,301 is a continuation of application No. 17/325,641, filed on May 20, 2021, granted, now 11,637,108, issued on Apr. 25, 2023.
Claims priority of provisional application 62/698,665, filed on Jul. 16, 2018.
Prior Publication US 2024/0357788 A1, Oct. 24, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10B 10/00 (2023.01); G06F 30/392 (2020.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10D 89/10 (2025.01)
CPC H10B 10/12 (2023.02) [G06F 30/392 (2020.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H10D 89/10 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A memory cell comprising:
a first pull up transistor;
a first pass gate transistor coupled to the first pull up transistor;
a second pull up transistor having a first active region extending in a first direction, and the first active region being located on a first level;
a second pass gate transistor having a second active region extending in the first direction, the second active region being located on the first level, and being separated from the first active region in a second direction different from the first direction, and the second active region being adjacent to the first active region, the second pass gate transistor being coupled to the second pull up transistor; and
a first metal contact extending in the second direction, and extending from the first active region to the second active region, the first metal contact being located on a second level different from the first level, the first metal contact electrically coupling a drain of the second pull up transistor to a drain of the second pass gate transistor;
wherein the first pass gate transistor, the second pass gate transistor, the first pull up transistor and the second pull up transistor are part of a four transistor (4T) memory cell.
 
8. A memory cell comprising:
a first pull down transistor having a first active region extending in a first direction, and the first active region being located on a first level;
a first pass gate transistor having a second active region extending in the first direction, the second active region being located on the first level, and being separated from the first active region in a second direction different from the first direction;
a second pull down transistor having a third active region extending in the first direction, the third active region being located on the first level, and being separated from the first active region in the first direction;
a second pass gate transistor having a fourth active region extending in the first direction, the fourth active region being located on the first level, being separated from the third active region in the second direction, and being separated from the second active region in the first direction; and
a first metal contact extending in the second direction, and extending from the first active region to the second active region, the first metal contact being located on a second level different from the first level, the first metal contact electrically coupling a drain of the first pull down transistor to a drain of the first pass gate transistor,
wherein the first pass gate transistor, the second pass gate transistor, the first pull down transistor and the second pull down transistor are part of a four transistor (4T) memory cell.
 
14. A memory cell comprising:
a first pull down transistor;
a first pass gate transistor coupled to the first pull down transistor;
a second pull down transistor having a first active region extending in a first direction, and the first active region being located on a first level;
a second pass gate transistor having a second active region extending in the first direction, the second active region being located on the first level, and being separated from the first active region in a second direction different from the first direction, the second pass gate transistor coupled to the second pull down transistor;
a first metal contact extending in the second direction, and extending from the first active region to the second active region, the first metal contact being located on a second level different from the first level, the first metal contact electrically coupling a drain of the second pull down transistor to a drain of the second pass gate transistor; and
wherein the first pass gate transistor, the second pass gate transistor, the first pull down transistor and the second pull down transistor are part of a four transistor (4T) memory cell.