US 12,408,315 B2
Flexible merge scheme for source/drain epitaxy regions
Kai-Hsuan Lee, Hsinchu (TW); Chia-Ta Yu, New Taipei (TW); Cheng-Yu Yang, Xihu Township (TW); Sheng-Chen Wang, Hsinchu (TW); Sai-Hooi Yeong, Zhubei (TW); Feng-Cheng Yang, Zhudong Township (TW); and Yen-Ming Chen, Chu-Pei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 22, 2023, as Appl. No. 18/517,275.
Application 16/206,183 is a division of application No. 15/492,142, filed on Apr. 20, 2017, granted, now 10,483,266, issued on Nov. 19, 2019.
Application 18/517,275 is a continuation of application No. 17/234,201, filed on Apr. 19, 2021, granted, now 11,856,743.
Application 17/234,201 is a continuation of application No. 16/669,736, filed on Oct. 31, 2019, granted, now 10,985,167, issued on Apr. 20, 2021.
Application 16/669,736 is a continuation of application No. 16/206,183, filed on Nov. 30, 2018, granted, now 10,529,725, issued on Jan. 7, 2020.
Prior Publication US 2024/0098959 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 62/13 (2025.01); H01L 21/027 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H10B 10/00 (2023.01); H10D 62/00 (2025.01); H10D 62/822 (2025.01); H10D 64/01 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10B 10/12 (2023.02) [H01L 21/0273 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H10B 10/18 (2023.02); H10D 62/021 (2025.01); H10D 62/151 (2025.01); H10D 64/021 (2025.01); H10D 84/013 (2025.01); H10D 84/0135 (2025.01); H10D 84/0158 (2025.01); H10D 84/0193 (2025.01); H10D 84/038 (2025.01); H10D 84/853 (2025.01); H10D 62/822 (2025.01); H10D 84/017 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
depositing a spacer layer comprising first portions on first semiconductor fins, and second portions on second semiconductor fins;
forming first fin spacers on opposing sides of the first semiconductor fins;
forming second fin spacers on opposing sides of the second semiconductor fins, wherein the second fin spacers are taller than the first fin spacers; and
performing an epitaxy process to simultaneously grow first epitaxy semiconductor regions based on the first semiconductor fins and second epitaxy semiconductor regions based on the second semiconductor fins, wherein when the first epitaxy semiconductor regions grown from neighboring ones of the first semiconductor fins start to merge with each other, the second epitaxy semiconductor regions grown from neighboring ones of the second semiconductor fins are separated from each other.