US 12,408,276 B2
Wiring substrate
Kensuke Matsuhashi, Nagoya (JP)
Assigned to NITERRA CO., LTD., Nagoya (JP)
Appl. No. 18/264,704
Filed by Niterra Co., Ltd., Nagoya (JP)
PCT Filed Apr. 8, 2022, PCT No. PCT/JP2022/017319
§ 371(c)(1), (2) Date Aug. 8, 2023,
PCT Pub. No. WO2022/224841, PCT Pub. Date Oct. 27, 2022.
Claims priority of application No. 2021-071065 (JP), filed on Apr. 20, 2021.
Prior Publication US 2024/0114629 A1, Apr. 4, 2024
Int. Cl. H05K 1/02 (2006.01); H05K 3/28 (2006.01); H05K 3/46 (2006.01)
CPC H05K 3/28 (2013.01) [H05K 1/0298 (2013.01); H05K 3/4673 (2013.01)] 3 Claims
OG exemplary drawing
 
1. A wiring substrate comprising:
an insulating substrate;
a surface metal layer provided on a surface of the insulating substrate and divided by a groove formed on the insulating substrate; and
a wiring layer disposed in an inner part of the insulating substrate,
wherein an insulating coat layer is provided around the groove,
wherein the wiring layer is disposed in such a manner that, as viewed from above, the wiring layer detours around a region where the groove is formed and a region where the insulating coat layer is formed so as not to overlap with the region where the groove is formed and the region where the insulating coat layer is formed, and
wherein an internal metal layer is further provided in an inner part of the insulating substrate, and the internal metal layer has an opening formed in a region which overlaps with the region where the groove is formed as viewed from above in such a manner that the opening contains the entirety of the region where the groove is formed.