US 12,408,263 B2
Differential pair inner-side impedance compensation
Lingyu Kong, Shanghai (CN)
Assigned to Dell Products L.P., Round Rock, TX (US)
Filed by Dell Products L.P., Round Rock, TX (US)
Filed on May 17, 2022, as Appl. No. 17/746,135.
Claims priority of application No. 202210419504.1 (CN), filed on Apr. 20, 2022.
Prior Publication US 2023/0345625 A1, Oct. 26, 2023
Int. Cl. H05K 1/02 (2006.01)
CPC H05K 1/0245 (2013.01) [H05K 1/025 (2013.01); H05K 2201/09236 (2013.01)] 17 Claims
OG exemplary drawing
 
1. An information handling system comprising:
a first differential pair on a printed circuit board of the information handling system, wherein the first differential pair includes:
first and second traces;
a first set of impedance compensations routed only on an inner-side of the first trace, wherein a first width of the first trace is increased at locations of each of the first impedance compensations; and
a second set of impedance compensations routed only on an inner-side of the second trace, wherein a second width of the second trace is increased at locations of each of the second impedance compensations, wherein the first and second impedance compensations are substantially aligned;
a second differential pair on the printed circuit board, the second differential pair includes third and fourth traces, wherein a first distance separates the first and second differential pairs based on a distance between an outer-edge of the second trace at phase tuning bumping areas of the first differential pair and an outer-edge of the third trace at phase tuning bumping areas of the second differential pair;
a third differential pair on the printed circuit board, the third differential pair includes fifth and sixth traces; and
a fourth differential pair on the printed circuit board, the fourth differential pair includes seventh and eighth traces, wherein a second distance separates the third and fourth differential pair based on a distance between an outer-edge of the sixth trace at the phase tuning bumping areas of the third differential pair and an outer-edge of the seventh trace at the phase tuning bumping areas of the fourth differential pair, wherein the first distance is greater than the second distance.