US 12,408,262 B2
Circuit board and method for manufacturing same
Do Hyuk Yoo, Seoul (KR); Seul Gi Lee, Seoul (KR); and Du Hyun Kim, Seoul (KR)
Assigned to LG INNOTEK CO., LTD., Seoul (KR)
Appl. No. 18/039,454
Filed by LG INNOTEK CO., LTD., Seoul (KR)
PCT Filed Nov. 26, 2021, PCT No. PCT/KR2021/017661
§ 371(c)(1), (2) Date May 30, 2023,
PCT Pub. No. WO2022/114859, PCT Pub. Date Jun. 2, 2022.
Claims priority of application No. 10-2020-0162806 (KR), filed on Nov. 27, 2020.
Prior Publication US 2024/0098884 A1, Mar. 21, 2024
Int. Cl. H05K 1/02 (2006.01); H05K 3/00 (2006.01); H05K 3/38 (2006.01); H05K 3/42 (2006.01)
CPC H05K 1/0242 (2013.01) [H05K 3/0055 (2013.01); H05K 3/381 (2013.01); H05K 3/0035 (2013.01); H05K 3/425 (2013.01); H05K 2203/072 (2013.01); H05K 2203/0723 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A circuit board comprising:
an insulating layer including an upper surface to which a surface roughness (Ra) is imparted; and
a via electrode disposed in a via hole of the insulating layer,
wherein the surface roughness (Ra) of the upper surface of the insulating layer satisfies a range of 110 nm to 190 nm,
wherein a difference between a maximum value and a minimum value of the surface roughness (Ra) imparted to the upper surface of the insulating layer is 40 nm or less,
wherein the surface roughness (Ra) of the upper surface of the insulating layer satisfies a range of 130 nm to 170 nm,
wherein a surface roughness (Ra) of a side surface of the via electrode satisfies a range of 120 nm to 200 nm,
wherein the maximum value is a maximum value of surface roughness (Ra) within a 1 mm*1 mm region of the upper surface of the insulating layer, and
wherein the minimum value is a minimum value of surface roughness (Ra) within the 1 mm*1 mm region.