US 12,408,247 B2
Adaptive loop technique for high PSRR current regulator
Christos Konstantopoulos, Padua (IT); Enrico Tonazzo, Villanova di Camposampiero (IT); Maurizio Galvano, Padua (IT); Mattia Montoncelli, Abano Terme (IT); and Federico Cusinato, Tombolo (IT)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on May 30, 2023, as Appl. No. 18/325,586.
Prior Publication US 2024/0407062 A1, Dec. 5, 2024
Int. Cl. H05B 45/30 (2020.01); G05F 1/46 (2006.01); G05F 1/565 (2006.01); H05B 45/345 (2020.01); H05B 45/48 (2020.01)
CPC H05B 45/345 (2020.01) [G05F 1/467 (2013.01); G05F 1/565 (2013.01); H05B 45/48 (2020.01)] 20 Claims
OG exemplary drawing
 
1. A circuit comprising adaptive loop circuitry, wherein the adaptive loop circuitry comprises:
a peak detector circuit configured to receive a sensed signal, rectify the sensed signal, and emit a continuous signal, Vpeak, wherein Vpeak is proportional to the peak of the rectified sensed signal;
an error amplifier with a first input element, a second input element, and an output element, wherein the first input element of the error amplifier is configured to receive the sensed signal; and
an output terminal configured to receive an output of the error amplifier added to a product of Vpeak multiplied by the output of the error amplifier.