| CPC H04W 74/0833 (2013.01) [H04W 74/0808 (2013.01)] | 12 Claims |

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6. A device comprising:
a processor circuit and a memory circuit, wherein the memory is arranged to store instructions for the processor circuit,
wherein the processor circuit is arranged to receive a random access response indicating a first backoff time interval of a first sub-band of a cell during a random access procedure,
wherein the processor circuit is arranged to receive a random access response indicating a second backoff time interval of a second sub-band of the cell during a random access procedure,
wherein the processor circuit is arranged to select a third backoff time interval for preamble retransmission of the random access procedure based on the first backoff time interval and the second backoff time interval,
wherein the processor circuit is arranged to perform a listen-before-talk procedure at a first time based on the third backoff time interval,
wherein the listen-before-talk procedure is performed on the first sub-band when the first backoff time interval is shorter than the second backoff time interval,
wherein the processor circuit is arranged to perform a second listen-before-talk procedure on the second sub-band based on the listen-before-talk procedure at a second time,
wherein the second time is based on the second backoff time interval,
wherein the second listen-before-talk procedure indicates that the first sub-band is occupied,
wherein the processor circuit is arranged to transmit a preamble in response to the second listen-before-talk procedure via the second sub-band,
wherein the preamble indicates that the second sub-band is available,
wherein there is no random access channel occasion on the first sub-band between the first time and the second time.
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