| CPC H04R 5/04 (2013.01) [G06F 3/162 (2013.01); H04R 3/14 (2013.01); H04S 3/008 (2013.01); H04S 7/304 (2013.01); H04R 5/033 (2013.01); H04S 2400/01 (2013.01); H04S 2400/11 (2013.01); H04S 2400/13 (2013.01)] | 20 Claims |

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1. A chip architecture for an audio system, the chip architecture comprising:
a main processor;
an audio subsystem comprising:
a plurality of processors;
at least one audio input/output (I/O) interface;
at least one peripheral component; and
an audio bus that provides a plurality of channels for communicating a plurality of data streams between the main processor and the audio subsystem, wherein the plurality of data streams is capable of being transmitted and processed in parallel,
wherein the audio subsystem is programmed to:
receive at least one input data stream directly from the at least one audio I/O interface, the at least one peripheral component, or the main processor;
perform at least one pre-processing task on the at least one input data stream received from the at least one audio I/O interface, the at least one peripheral component, or the main processor;
transmit the at least one pre-processed input data stream to the main processor;
perform at least one intermediate-processing task on the at least one input data stream received from the at least one audio I/O interface, the at least one peripheral component, or the main processor;
transmit the at least one intermediate-processed input data stream to the main processor;
perform at least one post-processing task on the at least one input data stream received from the at least one audio I/O interface, the at least one peripheral component, or the main processor; and
transmit the at least one post-processed input data stream to the audio I/O interface.
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