US 12,407,959 B2
Adaptive data selection for DCG / DAG
Nobuhiro Yanagisawa, San Jose, CA (US); Hiroaki Ebihara, San Jose, CA (US); Hiroki Ui, Yokohama (JP); Naoki Kitazawa, Yokohama (JP); and Ryuichi Moriizumi, Kanagawa (JP)
Assigned to OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US)
Filed by OMNIVISION TECHNOLOGIES, INC., Santa Clara, CA (US)
Filed on Dec. 22, 2023, as Appl. No. 18/394,861.
Prior Publication US 2025/0211878 A1, Jun. 26, 2025
Int. Cl. H04N 25/772 (2023.01); H03M 1/18 (2006.01)
CPC H04N 25/772 (2023.01) [H03M 1/186 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A pixel circuit, comprising:
a pixel array comprising a plurality of pixels;
a plurality of analog to digital converters (ADCs), wherein during a pixel data readout the plurality of ADCs is communicatively coupled to a respective plurality of pixels to receive image data from the respective pixel of the plurality of pixels;
a plurality of judge blocks, wherein each judge block is communicatively coupled to a respective ADC of the plurality of ADCs and wherein each judge block is configured to select and transmit gain data based on comparing an output of the respective ADC to a predetermined threshold for the respective ADC; and
an image signal processor (ISP) configured to:
receive outputs from the plurality of ADCs; and
combine the outputs of the plurality of ADCs to produce a combined converted value for the respective pixel.