US 12,407,948 B2
Imaging circuitry with high frame rate edge detection
Gal Fadida, Odem (IL)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed on May 19, 2023, as Appl. No. 18/320,436.
Prior Publication US 2024/0388811 A1, Nov. 21, 2024
Int. Cl. H04N 25/443 (2023.01); H04N 25/673 (2023.01); H04N 25/701 (2023.01); H04N 25/708 (2023.01); H04N 25/74 (2023.01)
CPC H04N 25/443 (2023.01) [H04N 25/673 (2023.01); H04N 25/701 (2023.01); H04N 25/708 (2023.01); H04N 25/74 (2023.01)] 19 Claims
OG exemplary drawing
 
1. A sensor comprising:
an array of pixels arranged in rows and columns, wherein each pixel in the array of pixels comprises a subpixel circuit, a first subtraction circuit, and a second subtraction circuit;
a first horizontal signal line coupled to a first row of pixels in the array;
first horizontal odd switches along the first horizontal signal line, wherein the first horizontal odd switches are configured to activate in a first phase during which difference values from first pairs of neighboring subpixels in the first row are stored in a first portion of the first subtraction circuits in the first row; and
first horizontal even switches along the first horizontal signal line, wherein the first horizontal even switches are configured to activate in a second phase during which difference values from second pairs of neighboring subpixels in the first row are stored in a second portion of the first subtraction circuits, different than the first portion of the first subtraction circuits, in the first row.