| CPC H04L 67/562 (2022.05) [G06F 1/206 (2013.01); G06F 1/3206 (2013.01); G06F 1/324 (2013.01); G06F 11/1441 (2013.01); G06F 21/54 (2013.01); G06F 21/74 (2013.01); H04L 69/12 (2013.01); G06F 1/3287 (2013.01); G06F 21/76 (2013.01); G06F 2221/2149 (2013.01)] | 25 Claims |

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1. An apparatus, comprising:
an interface to receive, from a hardware accelerator, an instruction including an indication of a privileged component;
circuitry, the circuitry arranged to:
determine whether the instruction is invalid based on a configuration, the configuration to provide a set of security rules to determine whether the instruction complies with one or more security features of a system;
apply a restriction to the instruction based on a determination that the instruction is invalid;
determine a set of associated system management operations to restore the system to a secure operating state before receipt of the invalid instruction using state information stored in the configuration; and
perform the set of associated system management operations.
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