US 12,407,564 B2
Identifying and marking failed egress links in data plane
Chaitanya Kodeboyina, Los Altos, CA (US); John Cruz, Cupertino, CA (US); Steven Licking, San Jose, CA (US); and Michael E. Attig, Sunnyvale, CA (US)
Assigned to Barefoot Networks, Inc., Santa Clara, CA (US)
Filed by Barefoot Networks, Inc., Santa Clara, CA (US)
Filed on Oct. 26, 2023, as Appl. No. 18/495,590.
Application 18/495,590 is a continuation of application No. 17/723,243, filed on Apr. 18, 2022, abandoned.
Application 17/723,243 is a continuation of application No. 16/903,305, filed on Jun. 16, 2020, granted, now 11,310,099, issued on Mar. 30, 2022.
Application 16/903,305 is a continuation of application No. 16/048,202, filed on Jul. 27, 2018, abandoned.
Application 16/048,202 is a continuation of application No. 15/150,015, filed on May 9, 2016, granted, now 10,063,407, issued on Aug. 28, 2018.
Claims priority of provisional application 62/292,498, filed on Feb. 8, 2016.
Prior Publication US 2024/0056348 A1, Feb. 15, 2024
Int. Cl. H04L 41/0677 (2022.01); H04L 41/0654 (2022.01); H04L 45/28 (2022.01); H04L 45/42 (2022.01); H04L 45/64 (2022.01); H04L 45/745 (2022.01); H04L 49/00 (2022.01); H04L 49/55 (2022.01); H04L 69/22 (2022.01)
CPC H04L 41/0677 (2013.01) [H04L 41/0654 (2013.01); H04L 45/28 (2013.01); H04L 45/42 (2013.01); H04L 45/64 (2013.01); H04L 45/745 (2013.01); H04L 49/3063 (2013.01); H04L 49/555 (2013.01); H04L 69/22 (2013.01)] 36 Claims
OG exemplary drawing
 
1. An integrated circuit for use in association with a network switch in packet forwarding-related operations in a network, the integrated circuit comprising:
programmable packet data processing pipeline hardware for use in (1) parsing and identifying header field data of received packet data and (2) matching the header field data to programmable match-action table data to determine one or more packet processing-related actions that correspond to the header field data, the one or more packet processing-related actions to be carried out in processing of the packet data, the programmable packet data processing pipeline hardware comprising ingress pipeline hardware and egress pipeline hardware; and
shared buffer memory to be shared between the ingress pipeline hardware and the egress pipeline hardware for use in (1) storing at least one portion of the received packet data sent from the ingress pipeline hardware and (2) providing the at least one portion of the received packet data stored in the shared buffer memory to the egress pipeline hardware;
wherein: the ingress pipeline hardware and the egress pipeline hardware are configurable to comprise respective pluralities of pipelines;
when the integrated circuit is in operation:
the parsing, the identifying, and the programmable match-action table data are programmable based upon software-generated configuration data to be provided to the integrated circuit;
in event of failure of at least one path for packet data transmission, the integrated circuit is configurable to select, based upon at least one data structure maintained at a data plane of the integrated circuit, at least one alternative path for the packet data transmission, the at least one path and/or the at least one alternative path being configurable to correspond to multiple respective network hops from the network switch, wherein the at least one alternative path is for use in association with multi-path transmission;
the at least one data structure is configurable to indicate primary and alternative tunnel-related transmission paths for use in the packet data transmission; the integrated circuit is to implement the one or more packet processing-related actions;
the one or more packet processing-related actions are configurable to comprise:
one or more equal-cost multi-path routing operations;
the integrated circuit is configurable to generate flow-related information and statistics-related information usable in association with software-defined networking;
the flow-related information is configurable to comprise data flow rate information; and
the statistics-related information is configurable to comprise packet count information and/or byte count information.