US 12,407,557 B2
Power efficient crest factor reduction
Jaiganesh Balakrishnan, Bengaluru (IN); Aswath Vs, Bengaluru (IN); Sriram Murali, Bengaluru (IN); Sreenath Narayanan Potty, Bengaluru (IN); Sundarrajan Rangachari, Bengaluru (IN); Girish Nadiger, Bengaluru (IN); and Kapil Kumar, New Delhi (IN)
Assigned to TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed by TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)
Filed on Dec. 28, 2023, as Appl. No. 18/399,278.
Claims priority of application No. 202341031976 (IN), filed on May 5, 2023.
Prior Publication US 2024/0372767 A1, Nov. 7, 2024
Int. Cl. H04L 27/26 (2006.01)
CPC H04L 27/2614 (2013.01) 20 Claims
OG exemplary drawing
 
1. A circuit comprising:
crest factor reduction (CFR) circuitry including:
a peak neighborhood analyzer having a first terminal and a second terminal;
peak detection circuitry having a first terminal, a second terminal, and a third terminal; and
a controller having a first terminal and a second terminal, the first terminal of the controller coupled to the second terminal of the peak neighborhood analyzer, the second terminal of the controller coupled to the second terminal of the peak detection circuitry,
wherein the peak neighborhood analyzer is configured to:
receive an input signal at the first terminal of the peak neighborhood analyzer;
analyze the input signal to determine whether a peak larger than a target threshold is expected within an interval; and
provide a first control signal at the second terminal of the peak neighborhood analyzer responsive to determining that a peak larger than the target threshold is expected within the interval, and
wherein the controller is configured to:
receive the first control signal at the first terminal of the controller; and
gate a clock or data to the peak detection circuitry responsive to the first control signal.