US 12,407,549 B2
Output signal protocol
Ahmad Nour Halawani, Heidelberg (DE); and Emil Pavlov, Heidelberg (DE)
Assigned to Allegro MicroSystems, LLC, Manchester, NH (US)
Filed by Allegro MicroSystems, LLC, Manchester, NH (US)
Filed on Nov. 6, 2023, as Appl. No. 18/502,259.
Prior Publication US 2025/0150314 A1, May 8, 2025
Int. Cl. H03K 9/08 (2006.01); H04L 25/49 (2006.01)
CPC H04L 25/4902 (2013.01) 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first processor configured to generate a first signal including a modulated pulse width and first encoded data;
a second processor configured to generate a second signal including a modulated amplitude and second encoded data; and
an output controller configured to combine the first signal and the second signal to generate an output signal, wherein the pulse width of the output signal is indicative of the first data and the amplitude is indicative of the second data.