US 12,407,489 B2
Signal generation device and signal generation method
Hironori Yoshioka, Atsugi (JP); and Tatsuya Iwai, Atsugi (JP)
Assigned to ANRITSU CORPORATION, Atsugi (JP)
Filed by ANRITSU CORPORATION, Atsugi (JP)
Filed on Jun. 13, 2023, as Appl. No. 18/333,858.
Claims priority of application No. 2022-122608 (JP), filed on Aug. 1, 2022.
Prior Publication US 2024/0039688 A1, Feb. 1, 2024
Int. Cl. H04L 7/00 (2006.01); H04B 1/04 (2006.01); H04L 7/02 (2006.01); H04L 1/00 (2006.01); H04L 13/00 (2006.01); H04L 25/02 (2006.01); H04L 49/90 (2022.01)
CPC H04L 7/005 (2013.01) [H04B 1/04 (2013.01); H04L 7/02 (2013.01); H04L 1/0033 (2013.01); H04L 13/00 (2013.01); H04L 25/026 (2013.01); H04L 49/90 (2013.01)] 7 Claims
OG exemplary drawing
 
1. A signal generation device, comprising:
a parallel data output unit that outputs m×N-bit width parallel data;
a transceiver unit that converts the m×N-bit width parallel data outputted from the parallel data output unit into m-bit width parallel data and outputs the data; and
a phase synchronization control unit that controls the phase of the m-bit width parallel data outputted from the transceiver unit,
wherein
the transceiver unit has m transceivers that convert N-bit width parallel data out of the m×N-bit width parallel data into 1-bit width serial data,
each of the transceivers has:
a FIFO (First-In First-Out) that stores the N-bit width parallel data and reads out the N-bit width parallel data according to a read clock signal;
a PISO (Parallel-In Serial-Out) that converts the N-bit width parallel data read from the FIFO into the 1-bit width serial data;
a usage amount determination unit that executes usage amount determination process for determining whether the usage amount of the FIFO is equal to or greater than the usage amount threshold; and
a phase adjustment unit that performs a first phase adjustment process for decreasing the phase of the read clock signal by a predetermined amount and a second phase adjustment process for increasing the phase of the read clock signal by a predetermined amount,
the phase synchronization control unit performs:
the phase synchronization control unit has the usage amount determination unit perform a first usage amount determination process as the usage amount determination process, on the condition that the output of the serial data from each of the transceivers has started;
the phase synchronization control unit has the phase adjustment unit perform the first phase adjustment process, on the condition that the usage amount of the FIFO of each transceiver is determined to be greater than the usage amount threshold by the first usage amount determination process;
the phase synchronization control unit has the usage amount determination unit perform a second usage amount determination process as the usage amount determination process, on the condition that the count that the usage amount of the FIFO of each transceiver is consecutively determined by the first usage amount determination process to be less than the usage amount threshold reaches a first determination count;
the phase synchronization control unit has the phase adjustment unit perform the second phase adjustment process, on the condition that the usage amount of the FIFO of each of the transceivers is determined to be less than the usage amount threshold by the second usage amount determination process; and
the phase synchronization control unit has the phase adjustment unit complete the adjustment of the phase of the read clock signal, on the condition that the count that the usage amount of the FIFO of each of the transceivers is consecutively determined by the second usage amount determination process to be greater than the usage amount threshold reaches a second determination count.