US 12,407,488 B2
Quadrature divider error correction
Robert C. Schell, Chatham, NJ (US)
Assigned to Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed by Avago Technologies International Sales Pte. Limited, Singapore (SG)
Filed on Apr. 27, 2023, as Appl. No. 18/308,460.
Prior Publication US 2024/0364494 A1, Oct. 31, 2024
Int. Cl. H04L 7/00 (2006.01); H03L 7/093 (2006.01); H03L 7/099 (2006.01)
CPC H04L 7/0025 (2013.01) [H03L 7/093 (2013.01); H03L 7/0992 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A circuit comprising:
a frequency divider configured to receive a plurality of first frequency input clock signals and provide a plurality of second frequency output clock signals, wherein the plurality of second frequency output clock signals are lower in frequency than the plurality of first frequency input clock signals;
a phase detector configured to determine a difference between the plurality of second frequency output clock signals;
a low pass filter configured to measure a clock signal spacing error associated with the plurality of second frequency output clock signals based on the difference between the plurality of second frequency output clock signals and to generate one or more control signals in response to the clock signal spacing error; and
a control unit configured to generate one or more corrected first frequency input clock signals based on the one or more control signals, wherein the frequency divider is a quadrature divider.