| CPC H04L 5/0048 (2013.01) [H04L 1/12 (2013.01); H04L 1/1854 (2013.01); H04L 27/2656 (2013.01); H04L 27/2657 (2013.01); H04L 27/2675 (2013.01); H04W 56/002 (2013.01); H04L 5/0023 (2013.01); H04L 25/0202 (2013.01); H04W 84/12 (2013.01)] | 20 Claims |

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1. A processor comprising memory configured to cause the processor to perform operations comprising:
receive, from an access point device, a downlink orthogonal frequency division multiple access (OFDMA) frame;
determine, based on the downlink OFDMA frame, a dynamic uplink bandwidth allocation for a non-access point station (STA);
determine, based on whether the downlink OFDMA frame was successfully received, acknowledgement information responsive to the downlink OFDMA frame;
delay for a short interframe space (SIFS); and
after the SIFS, transmit, to the access point device and using the dynamic uplink bandwidth allocation for the STA, an uplink transmission comprising the acknowledgement information responsive to the downlink OFDMA frame, wherein the uplink transmission is synchronized with a second uplink transmission comprising second acknowledgement information responsive to the downlink OFDMA frame transmitted by a second STA.
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