| CPC H04B 10/40 (2013.01) [H04L 7/0016 (2013.01); H04L 7/02 (2013.01); H04B 10/07 (2013.01); H04B 10/07953 (2013.01); H04B 10/60 (2013.01); H04B 10/616 (2013.01)] | 16 Claims |
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1. A method for optimizing performance of an optical transceiver, the method comprising:
receiving an optical input and converting the optical input into electrical signals;
receiving a performance value and a reference clock of the electrical signals from a DSP (digital signal processing) part;
generating a plurality of clocks by using the reference clock;
determining ADC (analog-to-digital converter) sampling timings of a plurality of ADCs on the basis of phases of the plurality of clocks applied to the plurality of ADCs; and
compensating, on the basis of the determined ADC sampling timings, for differences in physical length between output signals of the plurality of ADCs,
wherein the plurality of clocks include a first clock, a second clock, a third clock, and a fourth clock, each having a different phase,
wherein the output signals include a first signal, a second signal, a third signal, and a fourth signal,
wherein the compensating comprises sequentially varying the phases of the first clock, the second clock, the third clock, and the fourth clock to compensate for differences in physical length of the first signal, the second signal, the third signal, and the fourth signal, and
wherein performance of the electrical signals is estimated using bit error rate.
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