US 12,407,366 B2
Coding circuit and memory device including the same
Chaehyeon Shin, Seoul (KR); Jongsun Park, Seoul (KR); and Munseon Jang, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR); and KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION, Seoul (KR)
Filed by SK hynix Inc., Icheon-si (KR); and KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION, Seoul (KR)
Filed on Mar. 28, 2024, as Appl. No. 18/620,595.
Claims priority of application No. 10-2023-0166841 (KR), filed on Nov. 27, 2023.
Prior Publication US 2025/0175195 A1, May 29, 2025
Int. Cl. H03M 13/00 (2006.01); H03M 13/11 (2006.01)
CPC H03M 13/1148 (2013.01) [H03M 13/1105 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A coding circuit comprising:
an encoder circuit configured to generate parity by applying input data to a parity generating matrix and generate input codeword by concatenating the input data and the parity; and
a decoder circuit configured to detect and correct an out-of-boundary 2-bit error using syndromes, the out-of-boundary 2-bit error corresponding to two 1-bit errors occurred at two symbols respectively among a plurality of symbols included in output codeword, the syndromes being generated by applying the output codeword to the parity generating matrix.