US 12,407,363 B2
Continuous-time delta-sigma modulator
Yan-Hui Wu, New Taipei (TW); Yao-Ming Lu, Taoyuan (TW); Tai-Cheng Lee, Taipei (TW); Chih-Lung Chen, Hsinchu (TW); and Sheng-Yen Shih, Hsinchu (TW)
Assigned to REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed by REALTEK SEMICONDUCTOR CORPORATION, Hsinchu (TW)
Filed on Nov. 27, 2023, as Appl. No. 18/519,104.
Claims priority of application No. 111149259 (TW), filed on Dec. 21, 2022.
Prior Publication US 2024/0213999 A1, Jun. 27, 2024
Int. Cl. H03M 1/46 (2006.01); H03M 1/06 (2006.01)
CPC H03M 1/462 (2013.01) [H03M 1/0604 (2013.01); H03M 1/0626 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A continuous-time delta-sigma modulator (CT-DSM) comprising:
a loop filter configured to generate a first intermediate signal according to an input signal, a feedback signal, and a compensation signal;
a pipelined successive-approximation register (SAR) analog-to-digital converter (ADC) coupled to the loop filter and configured to generate a first digital code, a second digital code, a first quantization error signal, and a second quantization error signal according to the first intermediate signal;
a feedback circuit coupled to the pipelined SAR ADC and configured to generate the feedback signal according to the first digital code, the first quantization error signal, and the second quantization error signal;
an excess loop delay (ELD) compensation circuit coupled to the feedback circuit and the loop filter and configured to generate the compensation signal according to at least one output signal of the feedback circuit; and
a logic circuit coupled to the pipelined SAR ADC and configured to generate an output digital code according to the first digital code and the second digital code.