US 12,407,359 B2
Successive approximation analog-to-digital converter for a PAM-(2N-2) receiver
Pen-Jui Peng, Hsinchu (TW); Yun-Cheng Jao, Hsinchu (TW); and Yen-Po Lin, Hsinchu (TW)
Assigned to NATIONAL TSING HUA UNIVERSITY, Hsinchu (TW)
Filed by National Tsing Hua University, Hsinchu (TW)
Filed on Nov. 27, 2023, as Appl. No. 18/519,646.
Prior Publication US 2025/0175185 A1, May 29, 2025
Int. Cl. H03M 1/10 (2006.01)
CPC H03M 1/1014 (2013.01) 5 Claims
OG exemplary drawing
 
1. A successive approximation analog-to-digital converter adapted to convert an analog input signal that is in a pulse amplitude modulation (PAM)-(2N−2) format into a digital output signal that is N-bits wide, where N≥3, said successive approximation analog-to-digital converter comprising:
a switch circuit adapted to receive a first input voltage and a second input voltage that cooperatively represent the analog input signal, operable in an ON state and an OFF state, and configured to permit transmission of the first input voltage and the second input voltage therethrough when operating in the ON state, and to prevent the transmission of the first input voltage and the second input voltage therethrough when operating in the OFF state;
a conversion circuit including
a first capacitor group including a first common node, and a number (N) of first capacitors each having a first terminal and a second terminal, said first common node being connected to said first terminals of said first capacitors, and being further connected to said switch circuit to receive the first input voltage, said first capacitors cooperatively outputting, at said first common node, a first comparison voltage that is equal to the first input voltage when said switch circuit operates in the ON state, and that varies according to voltages at said second terminals of said first capacitors when said switch circuit operates in the OFF state, and
a second capacitor group including a second common node, and a number (N) of second capacitors each having a first terminal and a second terminal, said second common node being connected to said first terminals of said second capacitors, and being further connected to said switch circuit to receive the second input voltage, said second capacitors cooperatively outputting, at said second common node, a second comparison voltage that is equal to the second input voltage when said switch circuit operates in the ON state, and that varies according to voltages at said second terminals of said second capacitors when said switch circuit operates in the OFF state;
a comparison circuit connected to said first common node and said second common node to receive the first comparison voltage and the second comparison voltage, and configured to compare the first comparison voltage and the second comparison voltage so as to generate a comparison output including a first comparison signal that is N-bits wide and a second comparison signal that is N-bits wide, where generation of a least significant bit of the first comparison signal and a least significant bit of the second comparison signal is related to two of said first capacitors and two of said second capacitors;
a register connected to said comparison circuit to receive the comparison output, and configured to generate the digital output signal based on the comparison output; and
a controller connected to said comparison circuit to receive the comparison output, further connected to said second terminals of said first capacitors and said second terminals of said second capacitors, and configured to, with respect to each of said first capacitors and said second capacitors, selectively provide one of a reference voltage and a ground voltage to said second terminal of said capacitor based on the comparison output;
wherein, when a number (N−1) of most significant bits of the first comparison signal have identical logic values, said controller provides the reference voltage and the ground voltage respectively to said two first capacitors that are related to the generation of the least significant bit of the first comparison signal and the least significant bit of the second comparison signal, and provides the reference voltage and the ground voltage respectively to said two second capacitors that are related to the generation of the least significant bit of the first comparison signal and the least significant bit of the second comparison signal; and when otherwise, said controller provides one of the reference voltage and the ground voltage to both of said two first capacitors that are related to the generation of the least significant bit of the first comparison signal and the least significant bit of the second comparison signal, and provides the other one of the reference voltage and the ground voltage to both of said two second capacitors that are related to the generation of the least significant bit of the first comparison signal and the least significant bit of the second comparison signal.