US 12,407,354 B2
Digital-to-analog converter and a method for reducing aging effects on components of the digital-to-analog converter
Daniel Gruber, St. Andrae (AT); Michael Kalcher, Villach (AT); and Alessandra Cangianiello, Villach (AT)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2021, as Appl. No. 17/645,462.
Prior Publication US 2023/0198533 A1, Jun. 22, 2023
Int. Cl. H03M 1/66 (2006.01); H03M 1/00 (2006.01); H03M 1/06 (2006.01)
CPC H03M 1/002 (2013.01) [H03M 1/0682 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A digital-to-analog converter (DAC) comprising:
a plurality of DAC cells; and
a controller configured to generate a control signal to drive the plurality of DAC cells for each clock cycle, wherein the controller is configured to generate the control signal to select a set of at least one DAC cell for an input code or for a standby mode of the DAC such that the selected set of at least one DAC cell to be active for the same input code or for the standby mode of the DAC change during a predetermined period of time, wherein an output of the DAC is less than or equal to a predefined threshold,
wherein during a normal operation of the DAC where the DAC generates the output based on the input code, the controller is configured to generate the control signal in a way that one or more low-indexed DAC cells are swapped with one or more high-indexed DAC cells such that the selected set of at least one DAC cell to be active for the same input code changes during the predetermined period of time.