US 12,407,353 B1
Phase lock loop having low clock jitters
Chia-Liang (Leon) Lin, Fremont, CA (US)
Assigned to REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed by Realtek Semiconductor Corp., Hsinchu (TW)
Filed on May 17, 2024, as Appl. No. 18/667,405.
Int. Cl. H03L 7/093 (2006.01)
CPC H03L 7/093 (2013.01) 12 Claims
OG exemplary drawing
 
1. A PLL (phase lock loop) comprising:
a clock multiplier configured to receive a reference clock and output a multiplied clock;
a phase detector configured to receive the multiplied clock and a divided clock and output a phase error signal;
a loop filter configured to receive the phase error signal and output a control signal;
a controllable oscillator configured to output an output clock in accordance with the control signal; and
a clock divider configured to receive the output clock and output the divided clock in accordance with a divisor value, wherein the clock multiplier is either a frequency doubler or a frequency quadrupler, and a frequency response of the loop filter comprises a first notch at a frequency of the reference clock and a second notch at twice the frequency of the reference clock.