CPC H03L 7/06 (2013.01) [H03K 5/22 (2013.01); H03K 21/00 (2013.01)] | 17 Claims |
1. A synchronization signal generation circuit, comprising:
a clock signal generator, configured to generate a reference clock signal; and
a first controller, coupled among a host end device and a plurality of first peripheral devices, wherein the host end device receives an input clock signal, the first controller generates a plurality of candidate clock signals through a plurality of counting operations based on the reference clock signal, and the first controller selectively transmits one of the candidate clock signals to each first peripheral device according to request information corresponding to each first peripheral device,
wherein the candidate clock signals and the input clock signal have mutually aligned start time points in each frame period.
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