US 12,407,346 B2
Switch and sampling circuit
Matthieu Desvergne, Claix (FR); Marc Sabut, Eybens (FR); Emmanuel Allier, Grenoble (FR); and Thierry Masson, Varces (FR)
Assigned to STMicroelectronics (Alps) SAS, Grenoble (FR); and STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed by STMicroelectronics (Grenoble 2) SAS, Grenoble (FR); and STMicroelectronics (Alps) SAS, Grenoble (FR)
Filed on Mar. 28, 2023, as Appl. No. 18/191,491.
Claims priority of application No. 2203241 (FR), filed on Apr. 8, 2022.
Prior Publication US 2023/0327666 A1, Oct. 12, 2023
Int. Cl. H03K 17/687 (2006.01); H03K 17/10 (2006.01); H03K 17/22 (2006.01)
CPC H03K 17/6871 (2013.01) [H03K 17/102 (2013.01); H03K 17/223 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A switch comprising:
a first MOS transistor comprising a source, a drain, a gate, and a channel-forming region, the source connected to the channel-forming region and coupled with a first terminal of the switch, the drain coupled with a second terminal of the switch, and the gate connected to a first node of the switch;
a diode coupling the first terminal with the first node;
a capacitive element coupling a third terminal of the switch with the first node, the third terminal being configured to receive a control signal for the switch; a discharge circuit coupling the first node with the first terminal, the discharge circuit configured to conduct only when a voltage between the first node and the first terminal is greater than or equal to a threshold; and
a buffer circuit connected between the third terminal and the capacitive element.