US 12,407,341 B2
Multi-stage digitally controlled delay line linearity enhancing by redundancy and randomization
Ahmed Safwat Mohamed Aboelenein Elmallah, San Jose, CA (US); Mohammed Mohsen Abdulsalam Abdullatif, San Jose, CA (US); and Tamer Mohammed Ali, San Jose, CA (US)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK INC., Hsinchu (TW)
Filed on Oct. 25, 2023, as Appl. No. 18/383,511.
Claims priority of provisional application 63/384,615, filed on Nov. 22, 2022.
Prior Publication US 2024/0171165 A1, May 23, 2024
Int. Cl. H03K 5/1252 (2006.01); H03K 5/00 (2006.01); H03M 1/82 (2006.01)
CPC H03K 5/1252 (2013.01) [H03M 1/82 (2013.01); H03K 2005/00058 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit for reducing fractional spurs, comprising:
a digital to time converter (DTC) comprising a plurality of delay stages electrically coupled to one another in series, configured such that each delay stage of the plurality of delay stages is binary switched till a total code exceeds cell range and then it is fully turned ON, and thereafter it is moved to the next stage, wherein the each delay stage comprises a digitally controlled delay line (DCDL), wherein each of the DCDL of the each delay stage has code-dependent integrated nonlinearity (INL), and wherein the maximal value of the INL occurs at a mid-code position of the each delay stage; and
an offset stage comprising another DCDL electrically coupled to the DTC in series, configured to generate random codes for each required time delay of the DTC to ensure the probability of landing at the mid-code position is reduced and landing point is kept as far away as possible from the mid-code position for every required time delay in the DTC, thereby improving the INL and therefore the fractional spurs.