US 12,407,338 B2
Frequency multiplier circuits having cross-coupled capacitors therein which support frequency multiplication
Seongsoo Park, Suwon-si (KR); Taewook Kim, Seoul (KR); Hyunwoong Lim, Seoul (KR); Taewan Kim, Suwon-si (KR); Hyungyu Kim, Suwon-si (KR); Jooik Chung, Suwon-si (KR); and Michael Choi, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR); and Industry-Academic Cooperation Foundation, Yonsei University, (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Apr. 19, 2023, as Appl. No. 18/303,502.
Claims priority of application No. 10-2022-0062315 (KR), filed on May 20, 2022; and application No. 10-2022-0111676 (KR), filed on Sep. 2, 2022.
Prior Publication US 2024/0007090 A1, Jan. 4, 2024
Int. Cl. H03K 5/00 (2006.01); H03K 17/687 (2006.01)
CPC H03K 5/00006 (2013.01) [H03K 17/6874 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A frequency multiplier, comprising:
a first transistor having a drain electrically coupled to a non-inverting output node of the frequency multiplier;
a second transistor having a drain electrically coupled to the drain of the first transistor and to the non-inverting output node;
a third transistor having a drain electrically coupled to an inverting output node of the frequency multiplier, and a source electrically coupled to a source of the first transistor;
a fourth transistor having a drain electrically coupled to the drain of the third transistor and to the inverting output node, and a source electrically coupled to a source of the second transistor;
a first capacitor having first and second terminals electrically coupled to a gate of the first transistor and an inverting input node of the frequency multiplier, respectively;
a second capacitor having first and second terminals electrically coupled to a gate of the second transistor and a non-inverting input node of the frequency multiplier, respectively;
a third capacitor having first and second terminals electrically coupled to a gate of the third transistor and the inverting input node, respectively;
a fourth capacitor having first and second terminals electrically coupled to a gate of the fourth transistor and the non-inverting input node, respectively;
a fifth capacitor having a first terminal electrically coupled to a first node, which electrically connects the source of the first transistor and the source of the third transistor together, and a second terminal electrically coupled to the non-inverting input node; and
a sixth capacitor having a first terminal electrically coupled to a second node, which electrically connects the source of the second transistor and the source of the fourth transistor together, and a second terminal electrically coupled to the inverting input node.