US 12,407,337 B2
Flip-flop circuit and method
Yung-Chen Chien, Hsinchu (TW); Xiangdong Chen, Hsinchu (TW); Hui-Zhong Zhuang, Hsinchu (TW); Tzu-Ying Lin, Hsinchu (TW); Jerry Chang Jui Kao, Hsinchu (TW); and Lee-Chung Lu, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 10, 2024, as Appl. No. 18/768,843.
Application 18/768,843 is a continuation of application No. 18/302,178, filed on Apr. 18, 2023, granted, now 12,047,079.
Application 18/302,178 is a continuation of application No. 17/338,199, filed on Jun. 3, 2021, granted, now 11,632,102, issued on Apr. 18, 2023.
Claims priority of provisional application 63/142,880, filed on Jan. 28, 2021.
Prior Publication US 2024/0364317 A1, Oct. 31, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 3/3562 (2006.01); H03K 3/012 (2006.01); H03K 3/037 (2006.01)
CPC H03K 3/35625 (2013.01) [H03K 3/012 (2013.01); H03K 3/0372 (2013.01); H03K 3/0375 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A flip-flop circuit comprising:
a first inverter configured to receive a first clock signal and output a second clock signal;
a second inverter configured to receive the second clock signal and output a third clock signal;
a master latch comprising a transmission circuit; and
a slave latch comprising a first feedback inverter, wherein
the first feedback inverter comprises a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and
the transmission circuit comprises a third transistor configured to receive the third clock signal.