US 12,407,336 B2
Flip flop circuit
Po-Chia Lai, Fremont, CA (US); and Stefan Rusu, Sunnyvale, CA (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 8, 2023, as Appl. No. 18/366,981.
Application 18/366,981 is a continuation of application No. 17/148,661, filed on Jan. 14, 2021, granted, now 11,764,766.
Claims priority of provisional application 63/059,258, filed on Jul. 31, 2020.
Prior Publication US 2023/0387895 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 3/037 (2006.01); G01R 31/3185 (2006.01); H03K 3/356 (2006.01); H03K 3/3562 (2006.01)
CPC H03K 3/35625 (2013.01) [G01R 31/318541 (2013.01); H03K 3/356008 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A flip flop circuit, comprising:
at least one determining portion including first and second determining portions, configured to receive at least one enable signal that activates one of the first and second determining portions and simultaneously deactivates the other of the first and second determining portions, and having determining inputs and determining outputs, the determining inputs configured to receive first master outputs and second master outputs, the at least one determining portion configured to provide at the determining outputs the first master outputs when the first determining portion is activated or the second master outputs when the second determining portion is activated; and
a slave portion connected to the determining outputs and configured to generate an output signal.