US 12,407,335 B2
Flip flop circuit
Po-Chia Lai, Fremont, CA (US); and Stefan Rusu, Sunnyvale, CA (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 8, 2023, as Appl. No. 18/366,970.
Application 18/366,970 is a division of application No. 17/148,661, filed on Jan. 14, 2021, granted, now 11,764,766.
Claims priority of provisional application 63/059,258, filed on Jul. 31, 2020.
Prior Publication US 2023/0378941 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03K 3/037 (2006.01); G01R 31/3185 (2006.01); H03K 3/356 (2006.01); H03K 3/3562 (2006.01)
CPC H03K 3/35625 (2013.01) [G01R 31/318541 (2013.01); H03K 3/356008 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A flip flop circuit, comprising:
a first master portion configured to operate at a first mode, to receive a first input, and to generate first master outputs;
a second master portion configured to operate at a second mode, to receive a second input, and to generate second master outputs different from the first master outputs;
a time borrowing circuit configured to delay a predetermined time of a clock signal to be received by the first master portion and the second master portion; and
a slave portion configured to receive the first master outputs or the second master outputs and to generate an output signal.