US 12,407,310 B2
Power efficient complementary amplifier and method thereof
Chia-Liang (Leon) Lin, Fremont, CA (US)
Assigned to REALTEK SEMICONDUCTOR CORP., Hsinchu (TW)
Filed by Realtek Semiconductor Corp., Hsinchu (TW)
Filed on Mar. 13, 2023, as Appl. No. 18/182,439.
Prior Publication US 2024/0313721 A1, Sep. 19, 2024
Int. Cl. H03F 1/22 (2006.01); H03F 1/56 (2006.01); H03F 3/45 (2006.01)
CPC H03F 3/45188 (2013.01) [H03F 1/223 (2013.01); H03F 1/565 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An amplifier comprising:
a transformer configured to transform an input signal received from a primary coil into a first transformed signal of a first bias voltage and a second transformed signal of a second bias voltage via a first secondary coil and a secondary coil, respectively;
a N-type dynamic bias circuit configured to receive the first transformed signal and output the first bias voltage in accordance with a first DC (direct current) voltage and a peak of the first transformed signal;
a P-type dynamic bias circuit configured to receive the second transformed signal and output the second bias voltage in accordance with a second DC voltage and a valley of the second transformed signal;
a N-type cascode amplifier configured to receive the first transformed signal and output a first output signal across a first load; and
a P-type cascode amplifier configured to receive the second transformed signal and output a second output signal across a second load, wherein: the N-type cascode amplifier and the P-type cascode amplifier share a common source node.