US 12,407,307 B2
Power amplification circuit, radio-frequency circuit, and communication device
Kenji Tahara, Kyoto (JP); Kenichi Shimamoto, Kyoto (JP); and Takashi Yamada, Kyoto (JP)
Assigned to MURATA MANUFACTURING CO., LTD., Kyoto (JP)
Filed by Murata Manufacturing Co., Ltd., Kyoto (JP)
Filed on Jun. 16, 2022, as Appl. No. 17/807,188.
Application 17/807,188 is a continuation of application No. PCT/JP2020/041763, filed on Nov. 9, 2020.
Claims priority of application No. 2020-019942 (JP), filed on Feb. 7, 2020.
Prior Publication US 2022/0311395 A1, Sep. 29, 2022
Int. Cl. H03F 1/02 (2006.01); H03F 1/30 (2006.01); H03F 3/195 (2006.01); H03F 3/24 (2006.01)
CPC H03F 3/245 (2013.01) [H03F 1/301 (2013.01); H03F 1/302 (2013.01); H03F 3/195 (2013.01); H03F 2200/318 (2013.01); H03F 2200/451 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A power amplification circuit configured to amplify a power of a radio-frequency signal, the power amplification circuit comprising:
a first transistor that has a first input terminal, a first output terminal, and a first ground terminal;
a second transistor that has a second input terminal, a second output terminal, and a second ground terminal, the second input terminal of the second transistor being connected to the first input terminal of the first transistor, and the second output terminal of the second transistor being connected to the first output terminal of the first transistor;
a third transistor that has a third input terminal, a third output terminal, and a third ground terminal, the third input terminal of the third transistor being connected to the first output terminal of the first transistor;
a fourth transistor that has a fourth input terminal, a fourth output terminal, and a fourth ground terminal, the fourth input terminal of the fourth transistor being connected to the third input terminal of the third transistor, and the fourth output terminal of the fourth transistor being connected to the third output terminal of the third transistor;
a first bias circuit connected to the first input terminal;
a second bias circuit connected to the second input terminal;
a third bias circuit connected to the third input terminal;
a fourth bias circuit connected to the fourth input terminal;
a first resistor connected between the first ground terminal and ground; and
a second resistor connected between the second ground terminal and ground,
wherein the second resistor has a resistance value greater than a resistance value of the first resistor.