US 12,407,302 B2
Power amplifier circuit
Toshikazu Terashima, Kyoto (JP); Yuri Honda, Kyoto (JP); and Takashi Yamada, Kyoto (JP)
Assigned to MURATA MANUFACTURING CO., LTD., Kyoto (JP)
Filed by Murata Manufacturing Co., Ltd., Kyoto (JP)
Filed on Feb. 11, 2022, as Appl. No. 17/650,674.
Claims priority of application No. 2021-021652 (JP), filed on Feb. 15, 2021.
Prior Publication US 2022/0263477 A1, Aug. 18, 2022
Int. Cl. H03F 1/02 (2006.01); H03F 1/30 (2006.01); H03F 1/56 (2006.01); H03F 3/21 (2006.01)
CPC H03F 1/302 (2013.01) [H03F 1/0222 (2013.01); H03F 1/565 (2013.01); H03F 3/211 (2013.01); H03F 2200/451 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A power amplifier circuit comprising:
a first transistor having a base coupled to an input terminal, a collector coupled to an output terminal, and an emitter coupled to ground;
a first resistance element;
a first bias circuit coupled to the base of the first transistor via the first resistance element, the first bias circuit being configured to supply a bias to the first transistor;
a second transistor having a base coupled to the input terminal, a collector coupled to the output terminal, and an emitter coupled to ground;
a second resistance element;
a second bias circuit coupled to the base of the second transistor via the second resistance element, the second bias circuit being configured to supply a bias to the second transistor; and
a first impedance circuit having a first end coupled between the base of the first transistor and the input terminal, and a second end coupled between the first bias circuit and the first resistance element, the first impedance circuit being configured to have an open state for a direct-current component of a signal passing through the first impedance circuit, and have a closed state for an alternating-current component of the signal passing through the first impedance circuit,
wherein the first end of the first impedance circuit is coupled to a first node, the first node being on a first wire connecting the input terminal and the base of the first transistor, and
wherein a distance of the first wire from the input terminal to the first node is more than 0.5 times a distance of the first wire from the input terminal to the base of the first transistor.