US 12,407,261 B2
Clock generation for multi-phase converters
Narendra Nath Gaddam, Milpitas, CA (US); and Shrinivasan Jaganathan, San Jose, CA (US)
Assigned to Empower Semiconductor, Inc., San Jose, CA (US)
Filed by Empower Semiconductor, Inc., San Jose, CA (US)
Filed on May 22, 2024, as Appl. No. 18/671,453.
Application 18/671,453 is a continuation of application No. 17/447,793, filed on Sep. 15, 2021, granted, now 12,034,371.
Claims priority of provisional application 63/079,010, filed on Sep. 16, 2020.
Prior Publication US 2024/0372472 A1, Nov. 7, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H02M 3/158 (2006.01); G05F 1/10 (2006.01)
CPC H02M 3/1584 (2013.01) [G05F 1/10 (2013.01); H02M 3/158 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A voltage regulator, comprising:
a first clock generator circuit arranged to receive a reference clock signal, and to generate M first clock signals, wherein each of the M first clock signals are phase separated by 360°/M;
N phase extrapolator circuits, wherein N is not equal to M;
a phase selector multiplexer arranged to provide one of the M first clock signals to each of the N phase extrapolator circuits;
wherein the N phase extrapolator circuits are arranged to generate N output clock signals based in part on the M first clock signals received from the phase selector multiplexer,
wherein each of the N output clock signals are phase separated by 360°/N; and
wherein each of the N phase extrapolator circuits comprises:
a ramp generator circuit arranged to receive one of the M first clock signals and to generate a ramp signal in response to the received first clock signal.