US 12,407,252 B2
Switching regulator and operation clock signal generator circuit and control method thereof
Chia-Jung Chang, Hsinchu (TW); Shao-Ming Chang, Keelung (TW); Tsan-He Wang, New Taipei (TW); Jiing-Horng Wang, Hsinchu (TW); and Yu-Pin Tseng, Miaoli (TW)
Assigned to Richtek Technology Corporation, Hsinchu (TW)
Filed by Richtek Technology Corporation, Hsinchu (TW)
Filed on Sep. 21, 2023, as Appl. No. 18/471,331.
Claims priority of application No. 111139087 (TW), filed on Oct. 14, 2022.
Prior Publication US 2024/0128868 A1, Apr. 18, 2024
Int. Cl. H02M 3/157 (2006.01); H02M 3/158 (2006.01)
CPC H02M 3/157 (2013.01) [H02M 3/158 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A switching regulator, comprising:
a power stage circuit, which is configured to operably switch at least one power switch therein according to one of a plurality pulse width modulation (PWM) signal during a normal operation period, so as to convert an input voltage to an output voltage;
a control circuit, which is configured to operably generate the PWM signal according to the output voltage and an operation clock signal during the normal operation period; and
an operation clock signal generator circuit, which is configured to operably generate a plurality of test clock signals during a clock determination period and generate the operation clock signal during the normal operation period, wherein the plurality of test clock signals correspond to the plurality of PWM signals, respectively; wherein the operation clock signal generator circuit includes:
a clock signal determination unit, which is configured to operably generate a clock determination signal according to a plurality of phase node voltages corresponding to the plurality of test clock signals and according to the plurality of PWM signals corresponding to the plurality of test clock signals during the clock determination period; and
a clock signal generation unit, which is configured to operably generate the plurality of test clock signals in accordance with a basic clock signal and a tolerable frequency range during the clock determination period, and is configured to operably generate the operation clock signal according to the clock determination signal during the normal operation period;
wherein when the switching regulator operates during the clock determination period in a discontinuous conduction mode (DCM), the control circuit alternatingly generates a plurality of PWM signals according to the plurality of test clock signals generated by the operation clock signal generator circuit and the output voltage, each PWM signal corresponding to one of the test clock signals, so that the power stage circuit generates corresponding phase node voltages at a phase node;
wherein among the plurality of test clock signals, the operation clock signal generator circuit selects one test clock signal corresponding to a minimum phase node voltage as the operation clock signal during the normal operation period.