| CPC H01L 25/16 (2013.01) [H01L 23/3128 (2013.01); H01L 24/06 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/48147 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49174 (2013.01)] | 18 Claims |
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1. A semiconductor package, comprising:
a first chip stack that includes a plurality of first semiconductor chips on a substrate, the plurality of first semiconductor chips is in an offset stack structure and stacked such that a connection region is exposed at a top surface of each of the plurality of first semiconductor chips;
a second semiconductor chip on the substrate and horizontally spaced apart from the first chip stack;
a spacer on the second semiconductor chip; and
a second chip stack that includes a plurality of third semiconductor chips on the first chip stack and the spacer, the plurality of third semiconductor chips is in an offset stack structure,
wherein each of the plurality of first semiconductor chips includes:
a first chip pad on the connection region; and
a first wire that extends between the first chip pad and the substrate,
wherein the first wire of an uppermost one of the plurality of first semiconductor chips is horizontally spaced apart from a lowermost one of the plurality of third semiconductor chips
wherein the plurality of first semiconductor chips that are vertically adjacent to each other are attached to each other through a plurality of first adhesion layers provided on bottom surfaces of the plurality of first semiconductor chips
wherein:
the spacer is attached through a second adhesion layer to a top surface of the second semiconductor chip,
the second semiconductor chip has a second wire that extends between the second semiconductor chip and the substrate from the top surface of the second semiconductor chip, a portion of the second wire being positioned in the second adhesion layer under the spacer, and
a thickness of the second adhesion layer is greater than a thickness of one of the plurality of first adhesion layers.
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