US 12,406,971 B2
Staggered dual-side multi-chip interconnect
Shuo Zhang, Shenzhen (CN); Eric Zhu, Shenzhen (CN); Minto Zheng, Shenzhen (CN); Michael Zhai, Chengdu (CN); Town Zhang, Jiujiang (CN); and Jie Ma, Shenzhen (CN)
Assigned to Nvidia Corp., Santa Clara, CA (US)
Filed by NVIDIA Corp., Santa Clara, CA (US)
Filed on Sep. 6, 2023, as Appl. No. 18/462,259.
Application 18/462,259 is a continuation of application No. 17/553,519, filed on Dec. 16, 2021, granted, now 11,798,923.
Prior Publication US 2023/0411365 A1, Dec. 21, 2023
Int. Cl. H01L 23/538 (2006.01); H01L 25/10 (2006.01); H01L 25/16 (2023.01); H05K 1/18 (2006.01)
CPC H01L 25/105 (2013.01) [H01L 23/5386 (2013.01); H01L 25/16 (2013.01); H05K 1/181 (2013.01); H01L 2225/107 (2013.01); H01L 2225/1094 (2013.01); H05K 2201/10015 (2013.01); H05K 2201/10522 (2013.01); H05K 2201/10545 (2013.01); H05K 2201/10704 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A device comprising:
a first circuit package mounted on a first side of a substrate; and
a second circuit package mounted on a second side of the substrate in a stacked and staggered layout with the first circuit package;
vias forming a direct vertical connection through the substrate between input/output (IO) pins of the first circuit package and IO pins of the second circuit package in a region of the substrate overlapped by the first circuit package and the second circuit package; and
wherein the IO pins of the first circuit package are located exclusively in rows extending end-to-end along a single side of the first circuit package, and the IO pins of the second circuit package are located exclusively in rows extending end-to-end along a single side of the second circuit package.