US 12,406,970 B2
Semiconductor package and method of bonding workpieces
Bingchien Wu, Hsinchu (TW); Wei-Jen Wu, New Taipei (TW); and Chun-Yen Lo, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 17, 2024, as Appl. No. 18/415,558.
Application 18/415,558 is a continuation of application No. 17/460,306, filed on Aug. 30, 2021, granted, now 11,908,843.
Prior Publication US 2024/0153931 A1, May 9, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/10 (2006.01); H01L 21/66 (2006.01); H01L 23/544 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/105 (2013.01) [H01L 22/20 (2013.01); H01L 23/544 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2223/54426 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1082 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first semiconductor device comprising a first alignment pattern having a plurality of first scale patterns arranged in a zigzag manner deviated from a first direction; and
a second semiconductor device mounted over the first semiconductor device and comprising a second alignment pattern having a plurality of second scale patterns arranged in a zigzag manner deviated from a second direction parallel to the first direction.