US 12,406,966 B2
Device with embedded high-bandwidth, high-capacity memory using wafer bonding
Khandker Nazrul Quader, Santa Clara, CA (US); Robert Norman, Pendleton, OR (US); Frank Sai-keung Lee, San Jose, CA (US); Christopher J. Petti, Mountain View, CA (US); Scott Brad Herner, Portland, OR (US); Siu Lung Chan, San Jose, CA (US); Sayeef Salahuddin, Walnut Creek, CA (US); Mehrdad Mofidi, San Jose, CA (US); and Eli Harari, Saratoga, CA (US)
Assigned to SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed by SUNRISE MEMORY CORPORATION, San Jose, CA (US)
Filed on Jul. 9, 2024, as Appl. No. 18/767,750.
Application 18/138,270 is a division of application No. 16/776,279, filed on Jan. 29, 2020, granted, now 11,670,620, issued on Jun. 6, 2023.
Application 18/767,750 is a continuation of application No. 18/138,270, filed on Apr. 24, 2023, granted, now 12,068,286.
Claims priority of provisional application 62/843,733, filed on May 6, 2019.
Claims priority of provisional application 62/803,689, filed on Feb. 11, 2019.
Claims priority of provisional application 62/798,673, filed on Jan. 30, 2019.
Prior Publication US 2024/0363592 A1, Oct. 31, 2024
Int. Cl. H01L 25/065 (2023.01); G06F 3/06 (2006.01); G06F 11/10 (2006.01); G06F 12/0802 (2016.01); G06N 3/02 (2006.01); G11C 16/04 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G06F 12/0802 (2013.01); G06N 3/02 (2013.01); H01L 25/50 (2013.01); G06F 2212/60 (2013.01); G06F 2212/72 (2013.01); G11C 16/0483 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01)] 67 Claims
OG exemplary drawing
 
1. An integrated circuit assembly, comprising:
a first integrated circuit die having (i) a semiconductor substrate having circuitry formed therein or formed at a planar surface of the semiconductor substrate; (ii) an interconnection layer formed above the planar surface, the interconnection layer having conductors that are configurable to electrically connect to the circuitry; (iii) an insulation layer formed over the planar surface semiconductor substrate and encapsulating the interconnecting layer; and (iv) one or more bonding pads exposed on a surface of the insulation layer, wherein the insulation layer has formed therein conductor-filled vias that electrically connect between the conductors in the interconnection layer and the bonding pads; and
a second integrated circuit die having an insulation layer of a predetermined thickness, the insulation layer encapsulating (i) a plurality of modular memory circuits, each comprising one or more 3-dimensional arrays of storage transistors; (ii) an interconnection layer of conductors; (iii) bonding pads exposed on a first surface and on a second surface of the insulation layer, wherein a portion of the bonding pads on the first surface are bonded to bonding pads of the first integrated circuit die; (iv) conductor-filled through vias each electrically connecting a bonding pad on the first surface to a corresponding bonding pad on the second surface; and (v) a data center circuit that configure the conductors of the interconnection layer to route data signals and control signals from one or more groups of the modular memory circuits to the conductor-filled through vias.