US 12,406,964 B2
Chip package and method of forming chip packages
Weiping Li, Shanghai (CN)
Assigned to Yibu Semiconductor Co., Ltd., Shanghai (CN)
Filed by Yibu Semiconductor Co., Ltd., Shanghai (CN)
Filed on Nov. 26, 2021, as Appl. No. 17/535,985.
Claims priority of application No. 202011352636.4 (CN), filed on Nov. 27, 2020; application No. 202011352638.3 (CN), filed on Nov. 27, 2020; and application No. 202011359780.0 (CN), filed on Nov. 27, 2020.
Prior Publication US 2022/0173074 A1, Jun. 2, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/5389 (2013.01); H01L 24/13 (2013.01); H01L 25/50 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A chip package, comprising:
a redistribution circuit;
a stack of chips coupled to the redistribution circuit, the stack of chips including a first chip and one or more second chips, wherein each chip of the stack of chips has a front side facing the redistribution circuit and chip contacts formed on the front side, wherein each chip of the stack of chips further has a backside facing away from the redistribution circuit and no chip contacts formed on the backside;
one or more first chip connectors, each first chip connector of the one or more first chip connectors having a top side facing away from the redistribution circuit, a bottom side facing the redistribution circuit, and through vias extending through the each first chip connector from the top side to the bottom side; wherein:
the first chip has respective first chip contacts coupled to the redistribution circuit without soldering;
a respective second chip of the one or more second chips has a first portion assembled on the backside of the first chip and a second portion assembled on the top side of a respective chip connector of the one or more first chip connectors, and the respective second chip has respective second chip contacts disposed on the second portion and coupled to the redistribution circuit via at least some of the through vias in the respective chip connector, wherein at least a portion of the first chip is sandwiched between the first portion of the respective second chip and a portion of the redistribution circuit; and
the redistribution circuit is formed on the front side of the first chip and the bottom side of each of the one or more first chip connectors.
 
12. A chip package, comprising:
a stack of chips including a first chip and one or more second chips assembled over the first chip such that a front side of the first chip faces away from the one or more second chips and a front side of each of the one or more second chips faces the first chip, the first chip having first chip contacts on the front side of the first chip, each respective second chip of the one or more second chips having respective second chip contacts on the front side of the respective second chip, wherein each chip of the stack of chips further has a backside opposite the front side thereof and no chip contacts formed on the backside;
one or more first chip couplers, each respective first chip coupler of the one or more first chip couplers having a first side, a second side opposite to the first side, respective first coupler contacts on the first side, respective second coupler contacts on the second side, and respective through vias coupling at least some of the respective second coupler contacts to at least some of respective first coupler contacts; and
a redistribution layer formed on the front side of the first chip and the first side of each of the one or more first chip couplers, and coupled to the first chip contacts of the first chip and first coupler contacts of each of the one or more first chip couplers without soldering;
wherein the respective second chip of the one or more second chips has a first portion assembled on the backside of the first chip and a second portion assembled on the second side of at least one of the one or more first chip couplers, and the respective second chip contacts are disposed on the second portion and coupled to the redistribution layer via the at least one of the one or more first chip couplers, and wherein at least a portion of the first chip is sandwiched between the first portion of the respective second chip and a portion of the redistribution layer.
 
17. A chip package, comprising:
a stack of chips including a first chip and one or more second chips assembled over the first chip such that a front side of the first chip faces away from the one or more second chips and a front side of each of the one or more second chips faces the first chip, the first chip having first chip contacts on the front side of the first chip, each respective second chip of the one or more second chips having respective second chip contacts on the front side of the respective second chip, wherein each chip of the stack of chips further has a backside opposite the front side thereof and no chip contacts formed on the backside;
chip couplers, each respective chip coupler of the chip couplers having a first side, a second side opposite to the first side, respective first coupler contacts on the first side, respective second coupler contacts on the second side, and respective through vias coupling at least some of the respective second coupler contacts to at least some of the respective first coupler contacts; and
a redistribution layer formed on the front side of the first chip and the first side of at least one of the chip couplers, and coupled to the first chip contacts of the first chip and first coupler contacts of the at least one of the chip couplers without soldering;
wherein the respective second chip of the one or more second chips has a first potion assembled on the back side of the first chip and a second portion on the second side of a respective chip coupler of the chip couplers, wherein the respective second chip contacts are disposed on the second portion and coupled to the redistribution layer via the respective chip coupler, and wherein at least a portion of the first chip is sandwiched between the first portion of the respective second chip and a portion of the redistribution layer.