US 12,406,962 B2
Power delivery through capacitor-dies in a multi-layered microelectronic assembly
Adel A. Elsherbini, Tempe, AZ (US); William J. Lambert, Chandler, AZ (US); Krishna Bharath, Phoenix, AZ (US); Shawna M. Liff, Scottsdale, AZ (US); Nicolas Butzen, Portland, OR (US); Georgios Dogiamis, Chandler, AZ (US); Gerald S. Pasdast, San Jose, CA (US); Vivek Kumar Rajan, Portland, OR (US); Sathya Narasimman Tiagaraj, San Jose, CA (US); and Timothy Francis Schmidt, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Nov. 19, 2021, as Appl. No. 17/531,374.
Prior Publication US 2023/0163098 A1, May 25, 2023
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 25/18 (2023.01)
CPC H01L 25/0652 (2013.01) [H01L 23/481 (2013.01); H01L 23/5223 (2013.01); H01L 24/08 (2013.01); H01L 25/18 (2013.01); H01L 2224/08145 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microelectronic assembly, comprising:
an integrated circuit (IC) die in a first layer; and
a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being coupled by conductive pathways in the IC die,
wherein:
the first layer and the second layer are coupled by interconnects, and
the IC die comprises capacitors and voltage regulator circuitry.